The present invention relates generally to computer systems, and more specifically, to a combined rank and linear address incrementing utility for computer memory test operations.
Server systems requiring extremely high reliability and availability must be capable of continually monitoring memory subsystems for errors, correcting data errors, and repairing hardware errors to prevent data corruption, system checkstops, and other types of failures. Server systems with large memory subsystems require the ability to verify functionality and initialize large blocks of memory at power on, initial machine load (IML) time. A large memory subsystem may include a number of similar memory configurations, such as number of similarly configured multi-chip memory boards, forming a large memory address space. Overall memory access times for the subsystem are usually optimized by grouping the physical memory elements (chips) into a number of ranks (groups of chips smaller than the full array committed to an individual memory board) and assigning different contiguous portions of the logical address space to different ranks. This ensures that that multiple physical ranks of memory are activated when accessing large continuous blocks of data stored in sequential addresses of the logical address space.
A complex and robust memory controller design is capable of reliably initializing (which may also be referred to as resetting or clearing), background testing (which may also be referred to as scrubbing), and running a variety of read-write test operations (which may also be referred to as self-test or pattern testing) a range of different memory configurations. Various types of testing operations are commonly referred to as built-in self-test (BIST), array BIST (ABIST), and logic BIST (LBIST) operations. These test operations allow data errors to be detected and corrected using error correction code (ECC) logic to prevent data integrity failures and system checkstops from arising due to repairable data errors.
Test operations may also detect unrecoverable hardware errors occurring in the memory devices, such as shorted bits and other types of chip failures. This allows the defective hardware elements to be deactivated (which may also be referred to as masking) before they result in serious data corruption and system failures. Sophisticated testing and analysis may also detect impending failures so that memory subsystems showing signs or patterns of errors indicating an increased likelihood of a major failure in near future can be repaired or replaced before major system failures occur.